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PRELIMINARY
IEEE1394 LINK Layer / PCI Bridge LSI
Overview The CXD1947Q is a single-chip implementation of the link layer protocol of the 1394 Serial Bus, with additional features to support the transaction and bus management layers. The CXD1947Q includes a PCI bus interface and multiple DMA engines to enable high performance bus transfers. Features 1394 Link Layer/PCI Bridge Conforms to IEEE1394 high speed Serial Bus Supports 100Mb/s and 200Mb/s 1394 bus speeds Conforms to PCI version 2.1 specification Supports 6 independent programmable DMA channels -- Asynchronous transmit (1) -- Asynchronous receive (1) -- Isochronous transmit (2) -- Isochronous receive (2) * Three 128-word-deep FIFOs -- Asynchronous transmit -- Isochronous transmit -- Receive Block Diagram
ITDMA ALIGN ITF
CXD1947Q
160 pin QFP
* * * * *
* Includes interfaces to -- 1394 PHY interface (CXD1944 or equivalent) -- ROM (64K x 8) -- Silicon Serial ROM * Supports big and little Endian data formats Device Structure Silicon gate CMOS IC Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature range Topr -20 to +75
V C
ATDMA MBIU PCI BUS PCI INF RDMA
ALIGN
ATF
RF ALIGN
LINK CORE
PHY
IRDMA
SSN INF
ROM INF
CNTL REG
MBIU: ITDMA: ATDMA: RDMA: IRDMA:
Master Bus Interface Isochronous Transmit DMA Asynchronous Transmit DMA Receive DMA Isochronous Receive DMA
ALIGN: ITF: ATF: RF: SSN INF:
Data Aligner Isochronous Transmit FIFO Asynchronous Transmit FIFO Receive FIFO Silicon Serial Number
PHY:
Link Layer/Physical Layer 1394 Interface ROM INF: ROM Interface CNTL REG: Control Registers
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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10/18/96
Preliminary
CXD1947Q
Pin Configuration
VSS CYCLEIN CYCLEOUT PHYDATA4 PHYDATA5 PHYDATA6 VDD VSS PHYDATA7 ROMAD0 ROMAD1 ROMAD2 NC ROMAD3 ROMAD4 ROMAD5 ROMAD6 VDD VSS NC ROMAD7 ROMOE ROMAD8 ROMAD9 VDD VSS ROMAD10 ROMAD11 SERIALDT ROMAD12 ROMAD13 ROMAD14 VSS VDD ROMAD15 ROMDT7 ROMDT6 ROMDT5 ROMDT4 VDD 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VDD PCIAD23 PCIAD22 PCIAD21 PCIAD20 VDD VSS NC PCIAD19 PCIAD18 PCIAD17 PCIAD16 VDD VSS NC PCIC_BE2 PCIFRAME PCIIRDY PCITRDY PCIDEVSEL VDD VSS NC PCISTOP PCILOCK PCIPERR PCISERR PCIPAR VDD VSS NC PCIC_BE1 PCIAD15 PCIAD14 PCIAD13 PCIAD12 NC PCIC_BE0 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VDD PHYDATA3 PHYDATA2 PHYDATA1 PHYDATA0 PCTL1 VSS VDD LPSTAT PCTL0 LREQ DIRECT SCLK VSS VDD NC RESET PCICLK PCIGNT PCIREQ VSS VDD NC PCIAD31 PCIAD30 PCIAD29 PCIAD28 VSS VDD NC PCIAD27 PCIAD26 PCIAD25 PCIAD24 VDD VSS NC PCI_BE3 PCIIDSEL VSS
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
160 PIN QFP
VSS ROMDT3 ROMDT2 VSS VDD NC ROMDT1 ROMDT0 NC NC VSS VDD VST TDO TENA1 TDI TCK BCI VSS VDD PCIAD0 PCIAD1 PCIAD2 PCIAD3 VSS VDD NC INT PCIAD4 PCIAD5 PCIAD6 PCIAD7 VSS VDD NC PCIAD8 PCIAD9 PCIAD10 PCIAD11 VDD
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Preliminary
CXD1947Q
Functions 1. Asynchronous Function The CXD1947Q can transmit and receive all of the defined 1394 packet formats. Packets to be transmitted are read out of host memory and received packets are written into host memory, both using DMA. CXD1947Q can be programmed to act as a bus bridge between PCI and 1394 by directly executing 1394 read and write requests to the first 4GB of node offset address as read and writes to PCI memory space. The CXD1947Q can also be programmed to automatically place the data from read response packets in the proper location in host memory, then optionally interrupt the host processor to indicate that the transaction is complete. 2. Isochronous Function The CXD1947Q is capable of performing the cycle master function as defined by 1394. This means it contains a cycle timer and counter, and can transmit a special packet called a "cycle start" after every rising edge of the 8KHz cycle clock. The CXD1947Q can either generate the cycle clock from the 49.152MHz clock it receives from the PHY, or use the "CycleIn" pin directly. When not the cycle master, the CXD1947Q keeps its internal cycle timer synchronized with the cycle master node by correcting its own cycle timer with the reload value from the cycle start packet. The CXD1947Q supports two isochronous transmit channels and two isochronous receive channels. The CXD1947Q can regulate the rate of transmit to emulate data rates which are synchronous with, but not even multiples of, the 8KHz cycle clock. 3. PCI Interface This block acts both as a master and a slave on the PCI bus. As a slave, it decodes and responds to accesses to registers within CXD1947Q. As a master, it acts on behalf of the DMA units to generate transactions on the PCI bus. These transactions are used to move streams of data between system memory and the devices, as well as to read and write the DMA command lists. 4. DMA The CXD1947Q supports six independent DMA channels: one Asynchronous Transmit channel, one Asynchronous Receive channel, and four Isochronous channels. The CXD1947Q also has Physical DMA capability to respond to incoming requests to physical
addresses. The DMA unit is made up of three controller modules which support these various DMA functions. Each module has access to the PCI Interface to perform move operations, and is capable of sequencing through buffer descriptor lists stored in main memory in order to find the next buffer address after a channel exhausts the previous buffer. This frees the system from stringent interrupt response requirements after buffer completions. Each DMA controller stores the current channel program pointers and the current context for each of its DMA channels. A 32-bit incrementer updates both the Channel Program Pointers and the current buffer pointers. A 16-bit decrementer is used to adjust the count values for the channels. These incrementers and decrementers will be shared if a Controller unit has multiple channels. 5. Miscelleneous Functions Upon detecting a bus reset, the CXD1947Q automatically turns off the asynchronous transmitter. The receiver remains on so that the CXD1947Q can receive PHY selfID packets during the self-ID process which immediately follows the 1394 bus reset. Following the bus reset operation, the CXD1947Q receives the new node ID from the PHY and updates its node ID register. Host system software must explicitly restart the transmitter, presumably after it has corrected the node addresses of any queued-up packets. The CXD1947Q has an interface to a Dallas Semiconductor Silicon Serial NumberTM chip. This interface retrieves a unique serial number which management software then uses to uniquely identify the node for which the CXD1947Q is attached on the 1394 interface. 6. Brief Hardware Description The block diagram shows the CXD1947Q and its connections in a host system. The CXD1947Q attaches to the host via PCI bus. PCI provides an inexpensive and moderatly high performance point for the connection of I/O devices. PCI is a 32-bit, multiplexed address/data bus, capable of performing 32-bit transfers at a rate of 33MHz.
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Preliminary
CXD1947Q
Package Outline
Unit: mm 160 pin QFP (Plastic)
31.2 0.2 28.0 0.2 120 81 80 0.15 +0.1 -0.05 0.1
121
160
41
1 0.3 0.1 0.13
M
40 0.65 3.45 0.25
0.15 0.1 (29.6) 0-10
-4-
0.8 0.2

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